Digital Receiver System

MODEL Reference No : S3-2CH-RCVR-2U

Specifications of Digital Receiver

Overall System Specifications

  • Input Impedance : 50 Ohm
  • Input Signal : Radar returns from mesosphere, stratosphere, troposphere and ionosphere regions of the earth’s atmosphere ( for Pulsed RF )
  • Input Signal Frequency : 53MHz – 96Mhz
  • Input Signal Pulse widths : 0.5µs to 32µs
  • Input Signal Bandwidth : Variable upto 4MHz
  • Input Signal Level Range : - 60 dBm to 10 dBm
  • Input Signal Dynamic Range : 70dB
  • Input noise level : - 8 dBm
  • Reference signal : 10MHz sine wave fibre optic
  • Ranging reference trigger : 500ns width
  • Ranging reference trigger PRF : Variable upto 10kHz
  • No. of Range observational Windows : Upto 4
  • Length of each observation window : 1µs (min) to 512 µs (maximum)
  • Total number of Range bins : 512 in all windows put together
  • Arithmetic : Two’s complement
  • Complete Reception Implemented : FPGA Spatan 3 , 4 million

Digital Front End

  • Mixer
  • Numerically Controlled Oscillator
  • Cyclic Integrator Comb (CIC) Filter
  • FIR Filter 1
  • FIR Filter 2

Mixers implement a numerical multiplication between the input signal and the NCO frequency. NCO frequency is set to the center frequency of the first down conversion effected by the ADC.

After frequency translation to baseband, downsampling is implemented in CIC filter. The CIC filter has five stages. By choosing to use either fourth/ fifth stage, the best available rolloff is obtained in the frequency domain. Downsampling values are to be chosen keeping in mind the range sampling requirement that results in the range bins.

The sampling frequency of ADC is programmable.

The overall frequency response of the DDC is such that the filter response in the passband is maximally flat.

Also the filter has sharp cutoff outside the passband.

Maximum tolerable ripple in the passband is 0.5dB and minimum attenuation in the stopband is 40dB.


  • Function : up to 5 stage
  • Decimation rate : maximum up to 4096
  • Input Gain adjust : upto2 ** -45
  • Output Gain adjust : upto 2** -8
  • Input Data : 32 bit fixed pt
  • Output Data : 32 bit fixed pt
  • Bypass option : provided


  • Function : 64 tap FIR filter
  • Input data : 32 bit fixed point
  • Coefficients word length : 18 bit fixed point
  • Maximum Input data rate : 4MSPS
  • Maximum output data rate : 4MSPS
  • Implementation : FPGA based
  • Bypass option : provided


  • Function : 32 tap FIR filter
  • Input data : 32 bit fixed point
  • Coefficients word length : 18 bit fixed point
  • Maximum Input data rate : 4MSPS
  • Maximum output data rate : 4MSPS
  • Implementation : FPGA based
  • Bypass option : provided


  • Function : 64 tap FIR filter
  • Input data : 32 bit fixed point
  • Coefficients word length : 64 bit
  • Coefficient lookup table : Circular buffer of upto 128 values
  • Coefficient refresh rate : Once every trigger
  • Coefficient refresh latency : 4µs maximum w.r.t. rising edge of trigger
  • Output data : 56 bit fixed point
  • Maximum Input data rate : 4MSPS
  • Maximum output data rate : 4MSPS
  • Implementation : FPGA based
  • Bypass option : provide

Coherent Integration

  • Function : Time domain integration of data for each range bin for specified number of integrations
  • Coherent Integrations : 1 to 4096
  • Input : 48 bit fixed point
  • Output : 60 bit fixed point
  • Memory : 512 samples of I and Q (32bit)
  • Bypass option : provided

Common Synchronisation System for the Receivers

A common sine wave reference signal and ranging reference trigger will be supplied by USER.

  • Reference signal : 10 MHz Sinewave or fibre Optical
  • Reference signal level : minimum 0 dBm
  • Ranging reference Trigger : Signal with a pulse width of 500ns
  • Ranging reference trigger PRF : Variable upto 10kHz
  • Ranging reference Trigger level : 50 ohm drive TTL
  • Programmable delay adjustment range on each output of reference signal : 5µs
  • Programmable delay adjustment resolution on each output of reference signal : 10ns

Modes of Operation

Individual digital receivers can operate in any one of the following pre-programmed modes at any one time. Different digital receivers could operate in different modes.

Gated Sampling mode: Sampling will be done during pre-programmed time windows within each IPP. The starts of the windows will be defined with respect to a reference pulse that precedes each transmitted pulse. The widths of the windows could vary subject to a total of window widths of 512 microseconds. The minimum width of each window would be 1 microsecond. In this mode the maximum data rate occurs when the coherent integration block is bypassed. Taking 512 range bins of data every inter pulse period of 1ms the required maximum sustained data rate is worked out. Taking 32bits I channel data and 32 bits Q channel data outputs of the decoder the data rate is 8 bytes x 512 /1ms = 4 Mbyte/s. This data can be written to the hard disk on a sustained basis.

Triggered mode: (Pre trigger acquisition and post trigger acquisition): Data acquisition will be continuosly taking place into memory locations implemented as a double buffer. As soon as a trigger condition is met the data in the circular buffer and specified number of samples after the trigger will be recorded on the hard disk in the data recorder. For this mode an on-board memory is required to store the samples continuously till the trigger is received. It is envisaged that upto 4 seconds (programmable) of data before the trigger and upto 4 seconds (programmable) of data after the trigger will be recorded on the data recorder. Taking 100 range bins data every 1-millisecond IPP for I channel (32bits) and Q channel (32 bits) the onboard memory requirement for this mode works out to be (8 bytes * 100 range bins/1ms) * 4s = 3 MB. Such two buffers are required so that when the trigger occurs data in first full buffer will be transferred and acquisition will start on the second buffer.

A-Scope mode: In this mode it is required that the IF and quadrature data i.e., I and Q channel outputs, be available for viewing on an oscilloscope-like display located in the central room. This is required to monitor the time domain behaviour of received echoes on the antennas. A method of achieving this is provided by the DDC chip described above. The ISL5416 has a provision of bypassing any or all of its internal blocks such that the IF signal at the output of a chosen block is directly routed to the output. This feature could be used for the A-scope mode. It is envisaged that 32 bits of I and 32 bits of Q data at the rate of at least 4samples every microsecond will be transferred. Thus the data rate is 4bytes x 4 samples / 1 µs = 32 Mbytes per second. All this data need not be written to the hard disk. However user may require saving some snapshots interactively.

FDI mode: In this mode the NCO frequency will be required to change according to values in a circular memory buffer. A new frequency value will be loaded upon each trigger. The maximum data rate in this mode is same as that in case i) above.

Free running mode: In the free running mode the digital receiver will be acquiring data continuously. Final output of the digital receiver will be transferred to the host. In this mode, optional decoding and optional coherent integration will be available. The data could be optionally recorded on the acquisition system. In this mode the highest data rate results when the coherent integration block is bypassed. Taking the outputs of decoder viz., 32 bits of I channel and 32 bits of Q channel every microsecond the data rate works out to be 8 bytes/1µs = 8 Mbytes per second at a sustained rate. This data needs to be recorded to hard disk of the data recorder.

Data transfer will be initiated on the first ranging reference trigger and continue till a pre-specified time. Two types of integration are required in the free running mode:

a) Box-car integration with a programmable window length: In this method, the integration of samples within a window of specified length is done. Next sample is obtained by moving the window by one sample index. In this method, the result has the same number of points as the original.

b) N-point integration: Specified number of samples are integrated successively. In this method data reduction by a factor N results.

Specifications :

  • Channel : 1 no. *
  • Continuous DATA recording each channel : Maximum 8 Mbyte per sec
  • SATA HARDDISK size : 250GB
  • Link with PC : 1Gbit Fibre optic SX1000 ethernet

Internal Boards :

  • Digital Receiver board
  • AFE Module
    • RF maximum input 90Mhz
    • Sampling Frequency maximum 90 Mhz
    • 14 bit ADC
    • Max input Bandwidth<=5 Mhz
    • Input Frequency : 10Mhz clock
    • Output Frequency maximum 90Mhz
    • Input Pulse : TTL
    • Maximum Frequency 100Khz

Inputs :

  • RF inputs : SMA
  • Clock Source : TNC or Fibre optic SC type
  • Trigger Source : TNC or Fibre optic Sctype

Outputs :

  • Ethernet : Duplex SC Fibre optic SX1000 standard Multimode fibre
  • Enclosure
  • 2U 19” RACK Mount

Power Supply :

  • 230V / 300 WattsInternal Power Supply:
  • 1. ISOLATED Linear Power Supply for AFE Sampling Module

Associated Software :

  • Digital Receiver utility ver 1.0 rev 1.0 on CDROM